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課程名稱 |
交換電路與邏輯設計
Switching Circuit and Logic Design |
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開課學期 |
106-1 |
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授課對象 |
電機工程學系 |
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授課教師 |
盧奕璋 |
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課號 |
EE2012 |
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課程識別碼 |
901 32300 |
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班次 |
02 |
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學分 |
3.0 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四8(15:30~16:20)星期五8,9(15:30~17:20) |
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上課地點 |
博理113博理113 |
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備註 |
本系優先
總人數上限：120人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1061logic_design_lu |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Course Outline
1. Unit 1 Introduction: Number Systems and Conversion
2. Unit 2 Boolean Algebra
3. Unit 3 Boolean Algebra (continued)
4. Unit 4 Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. Unit 5 K-Maps
6. Unit 6 Quine-McClusky Method
7. Unit 7 Multi-Level Gate Circuits: NAND and NOR Gates
8. Unit 8 Combinational Circuit Design and Simulation Using Gates
9. Unit 9 Multiplexers, Decodes and PLD
10. Unit 11 Latches and FFs
11. Unit 12 Registers and Counters
12. Unit 13 Analysis of Clocked Sequential Circuits
13. Unit 14 Derivation of State Graphs and Tables
14. Unit 15 Reduction of State Tables-- State assignment
15. Unit 16 Sequential Circuit Design
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課程目標 |
Basic knowledges in Switching Circuits and Logic Design |
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課程要求 |
Quiz 1 & 2, Homework 1~7, Quartus II assignment 1 & 2, Midterm, Final |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
NA |
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參考書目 |
TEXTBOOK
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition, CENGAGE Learning. |
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評量方式
(僅供參考) |
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No. |
項目 |
百分比 |
說明 |
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1. |
Homework |
14% |
原始分數 |
2. |
Quiz 1 |
4% |
原始分數 |
3. |
Midterm |
35% |
原始分數 |
4. |
Quiz 2 |
4% |
原始分數 |
5. |
Quartus II |
6% |
原始分數 |
6. |
Final |
35% |
原始分數 |
7. |
Participation |
2% |
原始分數 |
8. |
等第制學期總成績 |
0% |
To receive A+, your raw score (原始分數加總) has to be within the top 8% among the total student body of four classes in whole. (依四班分佈調整後以等第給分) |
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週次 |
日期 |
單元主題 |
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第1週 |
9/14,9/15 |
Ch 1 Introdution, Number Systems … |
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第2週 |
9/21,9/22 |
Ch 2 Boolean Algebra |
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第3週 |
9/28,9/29 |
Ch 3 Boolean Algebra (Continued) |
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第4週 |
10/05,10/06 |
Ch 4 Applications of Boolean Algebra … |
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第5週 |
10/12,10/13 |
Ch 5 Karnaugh Maps; Ch 7 Multi-Level Gate Circuits … |
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第6週 |
10/19,10/20 |
Ch 7 Multi-Level Gate Circuits … ;
Quiz 1 on 10/20 |
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第7週 |
10/26,10/27 |
Ch 8 Combinational Ckt Design … |
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第8週 |
11/02,11/03 |
Ch 9 Multiplexers Decoders and PLDs |
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第9週 |
11/09,11/10 |
Review session on 11/02;
Midterm on 11/10 |
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第10週 |
11/16,11/17 |
Ch 11 Latches and FFs;
Combinational Ckt Design using Altera Quartus II
(Altera 課程講義 請至四班共同網頁下載) |
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第11週 |
11/23,11/24 |
Ch 11 Latches and FFs;
Ch 12 Registers and Counters |
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第12週 |
11/30,12/01 |
Ch 12 Registers and Counters;
Ch 13 Analysis of Clocked Sequential Ckts |
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第13週 |
12/07,12/08 |
Ch 13 Analysis of Clocked Sequential Ckts;
Sequential Ckt Design using Altera Quartus II
(Altera 課程講義 請至四班共同網頁下載) |
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第14週 |
12/14,12/15 |
Ch 14 Derivation of State Graphs and Tables |
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第15週 |
12/21,12/22 |
Ch 15 Reduction of State Tables (15.1 to 15.3);
Quiz 2 on 12/22 |
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第16週 |
12/28,12/29 |
Ch 16 Sequential Ckt Design (16.1 to 16.4) |
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第17週 |
1/04,1/05 |
Supplementary materials |
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第18週 |
1/11, 1/12 |
Review session on 1/11;
Final on 1/12 |
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